Architecture

A Digital Receiver Architecture for RFID Readers

by Roisah Fadhilah bt Saifullah

      This thesis discuss on digital receiver architecture for an RFID reader. Detection of the backscattered signals from the tags is the main problem in RFID reader design. This problem is due to the huge different scale of possible receiving powers. The detection performances become worse when it depends more on the environment. This is because, the reader with the carrier it need to send in order to supply the tags with energy is got obstructed by the very strong disturbances when it detect for a signals of the tags.  Thus, a new RFID receiver algorithm is introduced to fight the disturbances.

                A reader provides the communication link between the tags. Generally, there are 2 categories of RFID tags which are active and passive. Active tags carry their own power supply while the passive is not. They get the energy from the electromagnetic field released by the reader and react to its requests by backscatter modulation of the carrier. This means that even there is no data to be transferred to the tag, the reader still need to provide the energy in form of a continuous carrier (CC) signal. This is also applicable to those time periods, when the tag reacts to the request (T->R).

Figure 1: Basic RFID communication

      Figure 1 shows this condition on an example of a basic RFID communication. Continuous Carrier (CC) is always been transmit by the reader, except when the interrogation occurred (R->T), where the carrier is modulated. The tags again react to the reader (T->R) by backscattering the carrier after a certain idle period (time t₁).

      On the other hand, the drawback of that condition is a self interference occurred which typically will lower the signal strength. The detection performance at the receiver will degrade especially in industrial environments noise. Thus, a new algorithm is created and its execution on an FPGA is presented.

Reader Architecture 

      Below are the physical set up of the RFID testbed. 

Figure 2: Block Diagram of the rapid prototyping board.

      We can see from the figure 2, the underlying hardware for the reader implementation which consists of the rapid prototyping board. DSP from Texas Instruments (TMS320C6416) is the main reconfigurable components and used for protocol stack processing. While, Xilink Virtex II FPGA, full filling the signal processing task. In addition, it comes out with 2 digital to analogue converters (16 bits) and 2 analogue to digital converters (14 bits). The DSP is clocked with 600MHz and 40 MHz by a single oscillator for each FPGA, DACs, and ADCs. DSP is connects to a PC by ethernet interface and allowing external communication to an application running on PC. 

      Then, we move to another proposed RFID reader architecture named as FPGA Architecture. This architecture decomposed into transmit and receive paths. 

Figure 3: Block diagram of FPGA Architecture. 

      On the transmitter path, after the transmission sequence, both data encoder and multiplexer switch to continuous carrier mode. This will resulted on a stream of digital output before modulated by amplitude shift keying (ASK), up converted to 13.56MHz and then filtered by bandpass for pulse shaping. 

      While, on the receiver path, the signal is sampled with carrier suppression at the ADC and bandpass filter to reduced the noise bandwith. 5MHz is being set to the bandwith corresponding to 2.5MHz on each of the two sidebands. 

Reference

1) Angerer, Christoph,  Rupp, Markus,  "Advanced synchronisation and decoding in RFID reader receivers",  Radio and Wireless Symposium, 2009. RWS '09. IEEE, On page(s): 59 - 62,  Volume: Issue: , 18-22 Jan. 2009 Abstract |Full Text: PDF (2564KB)